/*
 * @Author: Laputa
 * @Version: V0.0
 * @Date: 2023-12-06 17:42:35
 * @LastEditors: Laputa
 * @LastEditTime: 2023-12-27 17:24:54
 * @Description: This file contains the functions prototypes for the CCM firmware library.
 *
 * Copyright (c) 2023 by Levetop, All Rights Reserved.
 */

#ifndef _LT168_CCM_H
#define _LT168_CCM_H

#include "LT168.h"

/*******************************************************************************
 * Definitions
 ******************************************************************************/

/* CCM WKUPC */
#define CCM_WKUPC_WKUPSEN_MASK       (0x7FFFFFFFU)
#define CCM_WKUPC_WKUPSEN_SHIFT      (0U)
#define CCM_WKUPC_WKUPSEN(x)         (((uint32_t)(((uint32_t)(x)) << CCM_WKUPC_WKUPSEN_SHIFT)) & CCM_WKUPC_WKUPSEN_MASK)

#define CCM_WKUPC_WKUPFILTEREN_MASK  (0x80000000U)
#define CCM_WKUPC_WKUPFILTEREN_SHIFT (31U)
#define CCM_WKUPC_WKUPFILTEREN(x)    (((uint32_t)(((uint32_t)(x)) << CCM_WKUPC_WKUPFILTEREN_SHIFT)) & CCM_WKUPC_WKUPFILTEREN_MASK)

/* CCM CPPDC */
#define CCM_CPPDC_PPDC_MASK  (0x0FF00000U)
#define CCM_CPPDC_PPDC_SHIFT (20U)
#define CCM_CPPDC_PPDC(x)    (((uint32_t)(((uint32_t)(x)) << CCM_CPPDC_PPDC_SHIFT)) & CCM_CPPDC_PPDC_MASK)

/* CCM QSPIXIPMCFR */
#define CCM_QSPIXIPMCFR_QSPI0_XIPEN_MASK         (0x100U)
#define CCM_QSPIXIPMCFR_QSPI0_XIPEN_SHIFT        (8U)
#define CCM_QSPIXIPMCFR_QSPI0_XIPEN(x)           (((uint32_t)(((uint32_t)(x)) << CCM_QSPIXIPMCFR_QSPI0_XIPEN_SHIFT)) & CCM_QSPIXIPMCFR_QSPI0_XIPEN_MASK)

#define CCM_QSPIXIPMCFR_QSPI0_DATA_ENCR_EN_MASK  (0x200U)
#define CCM_QSPIXIPMCFR_QSPI0_DATA_ENCR_EN_SHIFT (9U)
#define CCM_QSPIXIPMCFR_QSPI0_DATA_ENCR_EN(x)    (((uint32_t)(((uint32_t)(x)) << CCM_QSPIXIPMCFR_QSPI0_DATA_ENCR_EN_SHIFT)) & CCM_QSPIXIPMCFR_QSPI0_DATA_ENCR_EN_MASK)

#define CCM_QSPIXIPMCFR_QSPI1_XIPEN_MASK         (0x10000U)
#define CCM_QSPIXIPMCFR_QSPI1_XIPEN_SHIFT        (16U)
#define CCM_QSPIXIPMCFR_QSPI1_XIPEN(x)           (((uint32_t)(((uint32_t)(x)) << CCM_QSPIXIPMCFR_QSPI1_XIPEN_SHIFT)) & CCM_QSPIXIPMCFR_QSPI1_XIPEN_MASK)

#define CCM_QSPIXIPMCFR_QSPI1_DATA_ENCR_EN_MASK  (0x20000U)
#define CCM_QSPIXIPMCFR_QSPI1_DATA_ENCR_EN_SHIFT (17U)
#define CCM_QSPIXIPMCFR_QSPI1_DATA_ENCR_EN(x)    (((uint32_t)(((uint32_t)(x)) << CCM_QSPIXIPMCFR_QSPI1_DATA_ENCR_EN_SHIFT)) & CCM_QSPIXIPMCFR_QSPI1_DATA_ENCR_EN_MASK)

#define CCM_QSPIXIPMCFR_QSPI2_XIPEN_MASK         (0x1000000U)
#define CCM_QSPIXIPMCFR_QSPI2_XIPEN_SHIFT        (24U)
#define CCM_QSPIXIPMCFR_QSPI2_XIPEN(x)           (((uint32_t)(((uint32_t)(x)) << CCM_QSPIXIPMCFR_QSPI2_XIPEN_SHIFT)) & CCM_QSPIXIPMCFR_QSPI2_XIPEN_MASK)

#define CCM_QSPIXIPMCFR_QSPI2_DATA_ENCR_EN_MASK  (0x2000000U)
#define CCM_QSPIXIPMCFR_QSPI2_DATA_ENCR_EN_SHIFT (25U)
#define CCM_QSPIXIPMCFR_QSPI2_DATA_ENCR_EN(x)    (((uint32_t)(((uint32_t)(x)) << CCM_QSPIXIPMCFR_QSPI2_DATA_ENCR_EN_SHIFT)) & CCM_QSPIXIPMCFR_QSPI2_DATA_ENCR_EN_MASK)

/* CCM QSPIKEYR */
#define CCM_QSPIKEYR_QSPI_KEY_MASK  (0xFFFFFFFFU)
#define CCM_QSPIKEYR_QSPI_KEY_SHIFT (0U)
#define CCM_QSPIKEYR_QSPI_KEY(x)    (((uint32_t)(((uint32_t)(x)) << CCM_QSPIKEYR_QSPI_KEY_SHIFT)) & CCM_QSPIKEYR_QSPI_KEY_MASK)

/* CCM QSPIGPIOCR */
#define CCM_QSPIGPIOCR_QSPI0_SS_DI_MASK      (0x1U)
#define CCM_QSPIGPIOCR_QSPI0_SS_DI_SHIFT     (0U)
#define CCM_QSPIGPIOCR_QSPI0_SS_DI(x)        (((uint32_t)(((uint32_t)(x)) << CCM_QSPIGPIOCR_QSPI0_SS_DI_SHIFT)) & CCM_QSPIGPIOCR_QSPI0_SS_DI_MASK)

#define CCM_QSPIGPIOCR_QSPI1_SS_DI_MASK      (0x2U)
#define CCM_QSPIGPIOCR_QSPI1_SS_DI_SHIFT     (1U)
#define CCM_QSPIGPIOCR_QSPI1_SS_DI(x)        (((uint32_t)(((uint32_t)(x)) << CCM_QSPIGPIOCR_QSPI1_SS_DI_SHIFT)) & CCM_QSPIGPIOCR_QSPI1_SS_DI_MASK)

#define CCM_QSPIGPIOCR_QSPI2_SS_DI_MASK      (0x4U)
#define CCM_QSPIGPIOCR_QSPI2_SS_DI_SHIFT     (2U)
#define CCM_QSPIGPIOCR_QSPI2_SS_DI(x)        (((uint32_t)(((uint32_t)(x)) << CCM_QSPIGPIOCR_QSPI2_SS_DI_SHIFT)) & CCM_QSPIGPIOCR_QSPI2_SS_DI_MASK)

#define CCM_QSPIGPIOCR_QSPI0_SS_DO_MASK      (0x100U)
#define CCM_QSPIGPIOCR_QSPI0_SS_DO_SHIFT     (8U)
#define CCM_QSPIGPIOCR_QSPI0_SS_DO(x)        (((uint32_t)(((uint32_t)(x)) << CCM_QSPIGPIOCR_QSPI0_SS_DO_SHIFT)) & CCM_QSPIGPIOCR_QSPI0_SS_DO_MASK)

#define CCM_QSPIGPIOCR_QSPI1_SS_DO_MASK      (0x200U)
#define CCM_QSPIGPIOCR_QSPI1_SS_DO_SHIFT     (9U)
#define CCM_QSPIGPIOCR_QSPI1_SS_DO(x)        (((uint32_t)(((uint32_t)(x)) << CCM_QSPIGPIOCR_QSPI1_SS_DO_SHIFT)) & CCM_QSPIGPIOCR_QSPI1_SS_DO_MASK)

#define CCM_QSPIGPIOCR_QSPI2_SS_DO_MASK      (0x400U)
#define CCM_QSPIGPIOCR_QSPI2_SS_DO_SHIFT     (10U)
#define CCM_QSPIGPIOCR_QSPI2_SS_DO(x)        (((uint32_t)(((uint32_t)(x)) << CCM_QSPIGPIOCR_QSPI2_SS_DO_SHIFT)) & CCM_QSPIGPIOCR_QSPI2_SS_DO_MASK)

#define CCM_QSPIGPIOCR_QSPI0_SS_OBE_MASK     (0x10000U)
#define CCM_QSPIGPIOCR_QSPI0_SS_OBE_SHIFT    (16U)
#define CCM_QSPIGPIOCR_QSPI0_SS_OBE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_QSPIGPIOCR_QSPI0_SS_OBE_SHIFT)) & CCM_QSPIGPIOCR_QSPI0_SS_OBE_MASK)

#define CCM_QSPIGPIOCR_QSPI1_SS_OBE_MASK     (0x20000U)
#define CCM_QSPIGPIOCR_QSPI1_SS_OBE_SHIFT    (17U)
#define CCM_QSPIGPIOCR_QSPI1_SS_OBE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_QSPIGPIOCR_QSPI1_SS_OBE_SHIFT)) & CCM_QSPIGPIOCR_QSPI1_SS_OBE_MASK)

#define CCM_QSPIGPIOCR_QSPI2_SS_OBE_MASK     (0x40000U)
#define CCM_QSPIGPIOCR_QSPI2_SS_OBE_SHIFT    (18U)
#define CCM_QSPIGPIOCR_QSPI2_SS_OBE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_QSPIGPIOCR_QSPI2_SS_OBE_SHIFT)) & CCM_QSPIGPIOCR_QSPI2_SS_OBE_MASK)

#define CCM_QSPIGPIOCR_QSPI0_SS_PUE_MASK     (0x1000000U)
#define CCM_QSPIGPIOCR_QSPI0_SS_PUE_SHIFT    (24U)
#define CCM_QSPIGPIOCR_QSPI0_SS_PUE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_QSPIGPIOCR_QSPI0_SS_PUE_SHIFT)) & CCM_QSPIGPIOCR_QSPI0_SS_PUE_MASK)

#define CCM_QSPIGPIOCR_QSPI1_SS_PUE_MASK     (0x2000000U)
#define CCM_QSPIGPIOCR_QSPI1_SS_PUE_SHIFT    (25U)
#define CCM_QSPIGPIOCR_QSPI1_SS_PUE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_QSPIGPIOCR_QSPI1_SS_PUE_SHIFT)) & CCM_QSPIGPIOCR_QSPI1_SS_PUE_MASK)

#define CCM_QSPIGPIOCR_QSPI2_SS_PUE_MASK     (0x4000000U)
#define CCM_QSPIGPIOCR_QSPI2_SS_PUE_SHIFT    (26U)
#define CCM_QSPIGPIOCR_QSPI2_SS_PUE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_QSPIGPIOCR_QSPI2_SS_PUE_SHIFT)) & CCM_QSPIGPIOCR_QSPI2_SS_PUE_MASK)

#define CCM_QSPIGPIOCR_QSPI0_SS_GPIOEN_MASK  (0x20000000U)
#define CCM_QSPIGPIOCR_QSPI0_SS_GPIOEN_SHIFT (29U)
#define CCM_QSPIGPIOCR_QSPI0_SS_GPIOEN(x)    (((uint32_t)(((uint32_t)(x)) << CCM_QSPIGPIOCR_QSPI0_SS_GPIOEN_SHIFT)) & CCM_QSPIGPIOCR_QSPI0_SS_GPIOEN_MASK)

#define CCM_QSPIGPIOCR_QSPI1_SS_GPIOEN_MASK  (0x40000000U)
#define CCM_QSPIGPIOCR_QSPI1_SS_GPIOEN_SHIFT (30U)
#define CCM_QSPIGPIOCR_QSPI1_SS_GPIOEN(x)    (((uint32_t)(((uint32_t)(x)) << CCM_QSPIGPIOCR_QSPI1_SS_GPIOEN_SHIFT)) & CCM_QSPIGPIOCR_QSPI1_SS_GPIOEN_MASK)

#define CCM_QSPIGPIOCR_QSPI2_SS_GPIOEN_MASK  (0x80000000U)
#define CCM_QSPIGPIOCR_QSPI2_SS_GPIOEN_SHIFT (31U)
#define CCM_QSPIGPIOCR_QSPI2_SS_GPIOEN(x)    (((uint32_t)(((uint32_t)(x)) << CCM_QSPIGPIOCR_QSPI2_SS_GPIOEN_SHIFT)) & CCM_QSPIGPIOCR_QSPI2_SS_GPIOEN_MASK)

/* CCM MCURAMPRIOCR */
#define CCM_MCURAMPRIOCR_RAM512KP_MASK         (0x1U)
#define CCM_MCURAMPRIOCR_RAM512KP_SHIFT        (0U)
#define CCM_MCURAMPRIOCR_RAM512KP(x)           (((uint32_t)(((uint32_t)(x)) << CCM_MCURAMPRIOCR_RAM512KP_SHIFT)) & CCM_MCURAMPRIOCR_RAM512KP_MASK)

#define CCM_MCURAMPRIOCR_RAM256KP_MASK         (0x2U)
#define CCM_MCURAMPRIOCR_RAM256KP_SHIFT        (1U)
#define CCM_MCURAMPRIOCR_RAM256KP(x)           (((uint32_t)(((uint32_t)(x)) << CCM_MCURAMPRIOCR_RAM256KP_SHIFT)) & CCM_MCURAMPRIOCR_RAM256KP_MASK)

#define CCM_MCURAMPRIOCR_SYSRAM0ISOEN_MASK     (0x10000U)
#define CCM_MCURAMPRIOCR_SYSRAM0ISOEN_SHIFT    (16U)
#define CCM_MCURAMPRIOCR_SYSRAM0ISOEN(x)       (((uint32_t)(((uint32_t)(x)) << CCM_MCURAMPRIOCR_SYSRAM0ISOEN_SHIFT)) & CCM_MCURAMPRIOCR_SYSRAM0ISOEN_MASK)

#define CCM_MCURAMPRIOCR_SYSRAM1ISOEN_MASK     (0x20000U)
#define CCM_MCURAMPRIOCR_SYSRAM1ISOEN_SHIFT    (17U)
#define CCM_MCURAMPRIOCR_SYSRAM1ISOEN(x)       (((uint32_t)(((uint32_t)(x)) << CCM_MCURAMPRIOCR_SYSRAM1ISOEN_SHIFT)) & CCM_MCURAMPRIOCR_SYSRAM1ISOEN_MASK)

#define CCM_MCURAMPRIOCR_SYSRAM2ISOEN_MASK     (0x40000U)
#define CCM_MCURAMPRIOCR_SYSRAM2ISOEN_SHIFT    (18U)
#define CCM_MCURAMPRIOCR_SYSRAM2ISOEN(x)       (((uint32_t)(((uint32_t)(x)) << CCM_MCURAMPRIOCR_SYSRAM2ISOEN_SHIFT)) & CCM_MCURAMPRIOCR_SYSRAM2ISOEN_MASK)

#define CCM_MCURAMPRIOCR_SYSRAM3ISOEN_MASK     (0x80000U)
#define CCM_MCURAMPRIOCR_SYSRAM3ISOEN_SHIFT    (19U)
#define CCM_MCURAMPRIOCR_SYSRAM3ISOEN(x)       (((uint32_t)(((uint32_t)(x)) << CCM_MCURAMPRIOCR_SYSRAM3ISOEN_SHIFT)) & CCM_MCURAMPRIOCR_SYSRAM3ISOEN_MASK)

#define CCM_MCURAMPRIOCR_DISPLAYRAMISOEN_MASK  (0x100000U)
#define CCM_MCURAMPRIOCR_DISPLAYRAMISOEN_SHIFT (20U)
#define CCM_MCURAMPRIOCR_DISPLAYRAMISOEN(x)    (((uint32_t)(((uint32_t)(x)) << CCM_MCURAMPRIOCR_DISPLAYRAMISOEN_SHIFT)) & CCM_MCURAMPRIOCR_DISPLAYRAMISOEN_MASK)

#define CCM_MCURAMPRIOCR_CACHERAMISOEN_MASK    (0x200000U)
#define CCM_MCURAMPRIOCR_CACHERAMISOEN_SHIFT   (21U)
#define CCM_MCURAMPRIOCR_CACHERAMISOEN(x)      (((uint32_t)(((uint32_t)(x)) << CCM_MCURAMPRIOCR_CACHERAMISOEN_SHIFT)) & CCM_MCURAMPRIOCR_CACHERAMISOEN_MASK)

#define CCM_MCURAMPRIOCR_SYSRAM0PD_MASK        (0x1000000U)
#define CCM_MCURAMPRIOCR_SYSRAM0PD_SHIFT       (24U)
#define CCM_MCURAMPRIOCR_SYSRAM0PD(x)          (((uint32_t)(((uint32_t)(x)) << CCM_MCURAMPRIOCR_SYSRAM0PD_SHIFT)) & CCM_MCURAMPRIOCR_SYSRAM0PD_MASK)

#define CCM_MCURAMPRIOCR_SYSRAM1PD_MASK        (0x2000000U)
#define CCM_MCURAMPRIOCR_SYSRAM1PD_SHIFT       (25U)
#define CCM_MCURAMPRIOCR_SYSRAM1PD(x)          (((uint32_t)(((uint32_t)(x)) << CCM_MCURAMPRIOCR_SYSRAM1PD_SHIFT)) & CCM_MCURAMPRIOCR_SYSRAM1PD_MASK)

#define CCM_MCURAMPRIOCR_SYSRAM2PD_MASK        (0x4000000U)
#define CCM_MCURAMPRIOCR_SYSRAM2PD_SHIFT       (26U)
#define CCM_MCURAMPRIOCR_SYSRAM2PD(x)          (((uint32_t)(((uint32_t)(x)) << CCM_MCURAMPRIOCR_SYSRAM2PD_SHIFT)) & CCM_MCURAMPRIOCR_SYSRAM2PD_MASK)

#define CCM_MCURAMPRIOCR_SYSRAM3PD_MASK        (0x8000000U)
#define CCM_MCURAMPRIOCR_SYSRAM3PD_SHIFT       (27U)
#define CCM_MCURAMPRIOCR_SYSRAM3PD(x)          (((uint32_t)(((uint32_t)(x)) << CCM_MCURAMPRIOCR_SYSRAM3PD_SHIFT)) & CCM_MCURAMPRIOCR_SYSRAM3PD_MASK)

#define CCM_MCURAMPRIOCR_DISPLAYRAMPD_MASK     (0x10000000U)
#define CCM_MCURAMPRIOCR_DISPLAYRAMPD_SHIFT    (28U)
#define CCM_MCURAMPRIOCR_DISPLAYRAMPD(x)       (((uint32_t)(((uint32_t)(x)) << CCM_MCURAMPRIOCR_DISPLAYRAMPD_SHIFT)) & CCM_MCURAMPRIOCR_DISPLAYRAMPD_MASK)

#define CCM_MCURAMPRIOCR_CACHERAMPD_MASK       (0x20000000U)
#define CCM_MCURAMPRIOCR_CACHERAMPD_SHIFT      (29U)
#define CCM_MCURAMPRIOCR_CACHERAMPD(x)         (((uint32_t)(((uint32_t)(x)) << CCM_MCURAMPRIOCR_CACHERAMPD_SHIFT)) & CCM_MCURAMPRIOCR_CACHERAMPD_MASK)

#define CCM_MCURAMPRIOCR_RAMPRIOTEST_MASK      (0xC0000000U)
#define CCM_MCURAMPRIOCR_RAMPRIOTEST_SHIFT     (30U)
#define CCM_MCURAMPRIOCR_RAMPRIOTEST(x)        (((uint32_t)(((uint32_t)(x)) << CCM_MCURAMPRIOCR_RAMPRIOTEST_SHIFT)) & CCM_MCURAMPRIOCR_RAMPRIOTEST_MASK)

/* CCM EPORT2FCR */
/* look lt168_pin.h */

/**
 * @brief: Wakeup Source Enumeration
 */
typedef enum {
    CCM_Wakeup_EPORT0_0      = 0,  /*!< EPORT0_0 wakeup source */
    CCM_Wakeup_EPORT0_1      = 1,  /*!< EPORT0_1 wakeup source */
    CCM_Wakeup_EPORT0_2      = 2,  /*!< EPORT0_2 wakeup source */
    CCM_Wakeup_EPORT0_3      = 3,  /*!< EPORT0_3 wakeup source */
    CCM_Wakeup_EPORT0_4      = 4,  /*!< EPORT0_4 wakeup source */
    CCM_Wakeup_EPORT0_5      = 5,  /*!< EPORT0_5 wakeup source */
    CCM_Wakeup_EPORT0_6      = 6,  /*!< EPORT0_6 wakeup source */
    CCM_Wakeup_EPORT0_7      = 7,  /*!< EPORT0_7 wakeup source */
    CCM_Wakeup_EPORT1_0      = 8,  /*!< EPORT1_0 wakeup source */
    CCM_Wakeup_EPORT1_1      = 9,  /*!< EPORT1_1 wakeup source */
    CCM_Wakeup_EPORT1_2      = 10, /*!< EPORT1_2 wakeup source */
    CCM_Wakeup_EPORT1_3      = 11, /*!< EPORT1_3 wakeup source */
    CCM_Wakeup_EPORT1_4      = 12, /*!< EPORT1_4 wakeup source */
    CCM_Wakeup_EPORT1_5      = 13, /*!< EPORT1_5 wakeup source */
    CCM_Wakeup_EPORT1_6      = 14, /*!< EPORT1_6 wakeup source */
    CCM_Wakeup_EPORT1_7      = 15, /*!< EPORT1_7 wakeup source */
    CCM_Wakeup_WDT_Reset     = 16, /*!< WatchDog Reset wakeup source */
    CCM_Wakeup_Reset_Pin     = 17, /*!< Reset Pin wakeup source */
    CCM_Wakeup_JTAG_PowerOn  = 18, /*!< JTAG Power on request wakeup source */
    CCM_Wakeup_WDT_Interrupt = 19, /*!< WatchDog Interrupt wakeup source */
    CCM_Wakeup_I2C           = 20, /*!< I2C wakeup source */
    CCM_Wakeup_EPORT2_5      = 21, /*!< EPORT2_5 wakeup source */
    CCM_Wakeup_EPORT2_6      = 22, /*!< EPORT2_6 wakeup source */
    CCM_Wakeup_Comp0_IT      = 23, /*!< COMP0 Interrupt source */
    CCM_Wakeup_Comp1_IT      = 24, /*!< COMP1 Interrupt wakeup source */
    CCM_Wakeup_USB_Resume    = 25, /*!< USB Resume wakeup source */
    CCM_Wakeup_PVD_IT        = 26, /*!< PVD Interrupt wakeup source */
    CCM_Wakeup_RTC_IT        = 27, /*!< RTC Interrupt wakeup source */
    CCM_Wakeup_EPORT2_1      = 28, /*!< EPORT2_1 wakeup source */
    CCM_Wakeup_EPORT2_2      = 29, /*!< EPORT2_2 wakeup source */
    CCM_Wakeup_EPORT2_3      = 30  /*!< EPORT2_3 wakeup source */
} ccm_wakeup_source_te;

/**
 * @brief: PWM Pin Pull Down Configuration Enumeration
 */
typedef enum {
    CCM_PWM_Pin_PullDown_pwm1_0 = 20, /*!< PWM1_0 Pin */
    CCM_PWM_Pin_PullDown_pwm1_1 = 21, /*!< PWM1_1 Pin */
    CCM_PWM_Pin_PullDown_pwm1_2 = 22, /*!< PWM1_2 Pin */
    CCM_PWM_Pin_PullDown_pwm1_3 = 23, /*!< PWM1_3 Pin */
    CCM_PWM_Pin_PullDown_pwm0_0 = 24, /*!< PWM0_0 Pin */
    CCM_PWM_Pin_PullDown_pwm0_1 = 25, /*!< PWM0_1 Pin */
    CCM_PWM_Pin_PullDown_pwm0_2 = 26, /*!< PWM0_2 Pin */
    CCM_PWM_Pin_PullDown_pwm0_3 = 27  /*!< PWM0_3 Pin */
} ccm_pwm_pin_pulldown_te;

/**
 * @brief: QSPI CS Pin Type Enumeration
 */
typedef enum {
    CCM_QSPI_CS_GPIO_Disable = 0, /*!< QSPI CS Pin Auto Mode  */
    CCM_QSPI_CS_GPIO_Enable  = 1  /*!< QSPI CS Pin GPIO Mode  */
} ccm_qspi_cs_gpio_type_te;

/**
 * @brief: QSPI CS Pin Pullup Enumeration
 */
typedef enum {
    CCM_QSPI_CS_GPIO_NO_Pullup = 0, /*!< QSPI CS Pin No Pullup  */
    CCM_QSPI_CS_GPIO_Pullup    = 1  /*!< QSPI CS Pin Pullup */
} ccm_qspi_cs_pullup_te;

/**
 * @brief: QSPI CS Pin Direction Enumeration
 */
typedef enum {
    CCM_QSPI_CS_GPIO_Input  = 0, /*!< QSPI CS Pin Input  */
    CCM_QSPI_CS_GPIO_Output = 1  /*!< QSPI CS Pin Output */
} ccm_qspi_cs_direction_te;

/**
 * @brief: Chip SRAM Enumeration
 */
typedef enum {
    CCM_SYSRAM0    = 0, /*!< SYSRAM0 */
    CCM_SYSRAM1    = 1, /*!< SYSRAM1 */
    CCM_SYSRAM2    = 2, /*!< SYSRAM2 */
    CCM_SYSRAM3    = 3, /*!< SYSRAM3 */
    CCM_DISPLAYRAM = 4, /*!< DISPLAYRAM */
    CCM_CACHERAM   = 5, /*!< CACHERAM */
} ccm_sram_te;

/*!<---------------End of Definitions--------------->!*/

/*******************************************************************************
 * APIs
 ******************************************************************************/
/* WakeUp Source Control Function */
void CCM_WakeUp_Source_Cmd(ccm_wakeup_source_te source, FunctionState state);

/* PWM Pin Pull Down Control Function*/
void CCM_PWM_Pin_PullDown_Cmd(ccm_pwm_pin_pulldown_te pin, FunctionState state);

/* XIP Control Function */
void XIP_Cmd(qspi *target, FunctionState state);
void XIP_Data_Encryption_Cmd(qspi *target, FunctionState state);
void XIP_Encryption_Key(uint32_t key);

/* QSPI CS Pin Initialize */
void QSPI_CS_Init(qspi *target, ccm_qspi_cs_gpio_type_te type, ccm_qspi_cs_pullup_te pullup, ccm_qspi_cs_direction_te dir);
/* QSPI CS Pin Operation Function */
void QSPI_CS_GPIO_Write(qspi *target, BitStatus status);

/* Chip SRAM Shut Off Control */
void CCM_SRAM_ShutOff_Cmd(ccm_sram_te sram, FunctionState state);
#endif